There has been a trend, in recent years, for coupling memory with logic circuits, such as microprocessors. Integrating more on-die memory, such as larger caches, within a microprocessor is a power-efficient means of achieving higher performance from the microprocessor. Increasing memory on a microprocessor may provide a larger performance increase than any other optimization of the microprocessor, for a given power budget. The integration may include static random-access memory (SRAM) or dynamic RAM (DRAM) coupled with the microprocessor logic, on the same semiconductor wafer.
Because of the area consumed by six-transistor SRAM (6T SRAM) cells typically used in larger caches, the size of caches is limited to maintain a reasonable die size and manufacturing cost. Minimizing the additional cost of incorporating a denser memory cell than SRAM is preferred for enabling larger caches. Thus, system designers wanting to integrate memory with logic devices generally choose DRAM, which occupies less space on a semiconductor wafer.
Transistors make up the heart of both microprocessors and memories. The manufacturing of transistors has occurred along two distinct paths, one for microprocessors and other logic circuits (logic processing) and another for memories (memory processing). For logic processing, transistors are optimized to be as fast as possible, and thus follow trends such as using thinner oxides and shorter channels, in order to obtain as much performance out of the transistor as possible. Leakage from these transistors tends to get worse as the logic device get faster (currently, microprocessors are available in the GigaHertz range). Although leakage is undesirable, microprocessor manufacturers can survive with the leaky transistors because the microprocessor has a large power budget.
In contrast, for memory processing, the impetus to avoid leakage from the transistors is vital. For DRAM manufacturers, this means having a good capacitor, so as to maintain as high a retention time as possible. A capacitor is made up of a dielectric material sandwiched between two plates, which are usually made of metal. Dielectric materials are generally selected in reference to a value, k, which denotes the permittivity of the material, relative to a vacuum. Untreated silicon dioxide (SiO2), for example, has a k-value of 4. A material with a high k-value makes a better dielectric for a capacitor than a material with a low k-value, where like metals are used for the plates.
Because of the presence of capacitors in the DRAM, the transistors in the DRAMs may be poor performers, relative to the logic transistors. DRAM transistors, however, do not leak, which is critical to DRAM performance. Thus, the capacitors used in DRAM manufacture are made with additional processing. As the DRAM cell gets smaller and smaller, it becomes more difficult to create a capacitor with enough capacitance, since a larger capacitance per unit area is needed. To optimize the supplemental capacitance, additional processing may be employed. Such additional processing is outside the normal methodology employed during logic processing.
Dynamic RAM (DRAM) cells with one transistor and one capacitor, known as 1T-1C DRAMs, may be ten times smaller in area, as compared to SRAM cells. The manufacture of such 1T-1C DRAMS usually involves costly processing steps to make a capacitor that can store enough charge to maintain reasonable refresh times (typically, at least 25 fF). Recently, interest in DRAM gain cells, specifically two-transistor (2T) and three-transistor (3T) DRAMs, has been growing. While the 2T and 3T DRAMs are larger in area than 1T-1C DRAMs, they are less expensive to manufacture and more scalable to future device technologies, since they do not employ a fixed capacitor value.
One barrier to embedding DRAMs in a logic process is gate leakage. Cutting-edge microprocessors are typically designed with state-of-the-art transistors. Such transistors employ thin oxides to control short channel effects and increase gate capacitance for higher drive current. In present microprocessor designs, the gate oxide of transistors is so thin (three to five molecular layers thick) that a significant amount of gate leakage current flows through the microprocessor. The leakage current of such a transistor in a 2T or 3T DRAM gain cell drastically reduces its retention time.
Additionally, the distinct approaches taken to memory processing and logic processing have made it difficult to integrate memories within logic devices. In particular, the complexity of processing the capacitor within the DRAM has made incorporating DRAMs into logic devices difficult and expensive.
Thus, there is a continuing need to for a capacitor design to be used with a DRAM cell that overcomes the shortcomings of the prior art.